Apple, Cellular Baseband Design Verification Intern

As a Design Verification Intern, you'll be part of our silicon design group's verification efforts, helping ensure the quality and reliability of next-generation cellular systems. Working on baseband modems and RF link controllers for Apple's SoCs, you'll contribute to reusable UVM verification environments and help develop coverage-driven and directed test cases that validate complex IP and subsystem designs. You'll work closely with multi-functional teams and receive hands-on mentorship throughout the internship. This internship offers an opportunity to build expertise in cellular protocols, complex IP and subsystem architectures, fabric protocols, and debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures. You'll also explore how LLMs and ML-based tools can improve verification productivity.

Responsibilities

• Contribute to detailed test plans for components of the design, including use cases, in collaboration with multi-functional teams.
• Help create coverage-driven verification plans from specifications and work to achieve coverage targets.
• Develop components of UVM-based, reusable testbenches, such as stimulus, checkers, VIPs and reference models.
• Implement tests from RTL simulation bring-up onwards; report and debug failures.
• Run regressions and report verification progress against test plans and coverage metrics.
• Build Python-based automation to improve team productivity.
• Explore the use of Large Language Models (LLMs) and ML-driven workflows to improve the efficiency and quality of verification.
• Document your work and present your results to the team at the end of the internship.

Minimum Qualifications

• Currently enrolled in Masters in Electrical Engineering, Computer Engineering, Computer Science, Communications Engineering or a related field.
• Knowledge of digital design fundamentals and SystemVerilog / Verilog.
• Programming experience in C/C++ and/or Python.
• Understanding of verification concepts such as constrained-random testing and coverage-driven verification.
• Test planning and problem-solving skills.
• Fluent in English (written and verbal).

Preferred Qualifications

• Knowledge of UVM and SystemVerilog Assertions (SVA).
• Experience with SystemC and C/C++ modeling for design verification.
• Python or Perl scripting and automation experience.
• Knowledge of 4G/5G cellular physical layer operation (3GPP).
• Familiarity with bus fabrics and protocols such as AHB, AXI or NoC.
• Familiarity with embedded processor cores.
• Experience using LLMs to improve productivity, including prompt engineering and LLM workflow optimization.